封装
1.1 Introduction, Function and classification of packages
1.1.1 IntroE
Microsystems and the technologies they constitute are the building blocks of information technology. These systems require a set of fundamental technologies that include not only microelectronics but also photonics, MEMS, RF and wireless. For these functions to be integrated into systems, they have to be designed, fabricated, tested, cooled and reliability assured.
Microsystems: microminiaturized and integrated systems based on microelectronics, photonics, RF, micro-electro-mechanical systems (MEMS) and packaging technologies.
Packaging: the bridge that interconnects the ICs and other components into a system-level board to form electronic products
Microelectronics: typically refers to those micro devices, such as ICs, which are fabricated in sub-micron dimensions, and which form the basis of all electronic products
1.1.2 Functions
protect the encapsulated microsystems device from the environment;
provides pathways for various input and output signals, these pathways can be electrical, mechanical, chemical, optical, etc.; package allows the microsystems die to be more easily handled for assembly onto boards and into systems;
Designed as a mechanism to transport away the heat generated by the die, allowing the die temperature to be maintained at a desired level. Otherwise, microsystem devices can heat up during operation and can cause drift and/or reliability issues.
Protect and Preserve the quality of the product, provide Information to the customer, facilitate Transport and Distribution
1.2 Moore’s Law Prediction
The concept of Moore’s Law for Packaging or interconnections (MLP) that can be viewed as interconnecting and integrating smaller chips with the highest transistor density and highest performance at the lowest cost.
Just as Moore’s Law for ICs has two components:
the number of transistors
cost of each transistor.
Law predicts the IC integration to double every 18 months.
The latest update of the roadmap is posted on the ITRS website. Figure shows the ITRS roadmap for printed CMOS Moore‘s Law and beyond, which more recently has been called ―More than Moore‖ or its abbreviation, MtM.
1.3 MSP (Microsystems Packaging) overview
1.3.1 Three major technologies
Microelectronics, Photonics, MEMS and RF/Wireless Devices
Systems Engineering
Systems Packaging
Overlap of ICs and systems: Sub-Products子产品
Overlap of packaging and systems: incomplete system-level Boards(since Boards do not contain the devices)非智能系统级电路板
Overlap of ICs and Packaging: Packaged devices / IC Packaging
1.3.2 Examples of Microsystems Packaging and IC’s
Electronic product contains
(1) semiconductor devices such as ICs
(2) packaging to integrate these ICs and other devices into components
(3) system-level boards which integrate these components to form the system-level assemblies
Examples of system Packaging (a) Inside a computer, (b) Inside a Cellular Phone, and (c) Inside an Automobile
1.3.3 IC & System Packaging Overview
Microsystem packaging involves two major functions
1. at the IC or device level 第一级封装
involves interconnecting, powering, cooling and protecting ICs
2. at the system-level 第二级封装
involves interconnection of all these components to be assembled on the system-level board, called motherboard母板
1.3.4 Systems Packaging Involves Electrical, Mechanical and Materials Technologies
Electrical problems relate to
signal propagation btw the transistors
power distribution required to operate these transistors.
Electrical parameters such as R,C,L are always present and cause signal delays and signal distortions.
引线电阻引起电压降，增加渡越时间；
电源分配问题：开关噪声
The combination of power distribution through all levels of system packaging, and the use and fabrication of materials with the above diversity of properties, invariably lead to the development of thermomechanical stresses at every interface.
通过各级系统封装的功率分布的组合，以及具有上述特性多样性的材料的使用和制造，总是导致每个界面上的热机械应力的发展。
The signal and power distribution requires appropriate use of materials to form the system-level packaging hierarchy.
e.g. Power distribution requires metals of highest electrical conductivity for least voltage drop. Heat transfer requires materials of highest thermal conductivity.
1.4 The importance of microsystem packaging
1.4.1 Every IC and Device Has to Be Packaged
All of ICs and devices have to be packaged at the IC-level to form IC packages, and at system-level to form system-level boards.
1.4.2 Controls Performance of Computers
The num of ICs and their interconnections required to form a processor/CPU determine the cycle-determining path from IC through package interconnections, thus control the speed / clock freq of CPU
1.4.3 Controls Size of Electronics
The num and size of ICs in a given system, such as a cellular phone, tend to be small.
1.4.4 Controls Reliability of Electronics
Solid-state devices such as ICs are extremely reliable, with failure rates in parts-per million (ppm). The failure mainly due to the packaging of devices
1.4.5 Controls Cost of Electronic Products
The cost of producing today’s ICs and MEMS devices is low due to a variety of factors such as large-scale and high throughput wafer starts-per-day and automation. However, system-level packaging cost. With all the packaging components to form system-level boards, si much higher
1.4.6 Required in Nearly Everything
Electronics are now a part of nearly all industries such as automotive, telecommunication, computer, consumer, medical, aerospace and military
1.5 Previous, future development in packaging technology
1.5.1 ME: The First Technology Wave
The invention of the transistor in 1949 by Brattain, Bardeen and Shockley at Bell Labs. The development of planar transistor technology by Bob Noyce in 1959
The first integrated circuit (IC), which incorporated two transistors and a resistor, developed by Jack Kilby in 1959.
The microsystems packaging as starting with a wafer and ending up with a finished system like a cellular phone. This is a very good example of technologies and systems in the 20th century.
1.5.2 RF and Wireless: The Second Technology Wave
A whole new industry has emerged with applications that span AM and FM radio to cellular phone to satellite to microwave communications, across the entire electromagnetic spectrum.
The main advantage of wireless is the fact that it cuts the cables. If the wireless equipment is small enough that it can actually be carried around everywhere. This is where Systems packaging applies. Wireless technology is also increasingly used for non-communications functions (GPS).
1.5.3 Photonics: The Third Technology Wave
Highly transparent fibers, and semiconductor lasers that established the feasibility of fiber optic communications. These discoveries are the fundamental building block technologies of today’s Internet networks.
Fortunately, we have a ways to go to reach the data transport limit of fiber. For example, with the current state of device technology, a good laser source can emit 10 photons/s, and a good detector—which can detect a bit with 10 photons on a single fiber.
Fiber optics is a future-proof technology. With wavelength-division multiplexing (WDM), it is now possible to transmit different colors of light over the same fiber. Thus, optics will play a key role in next-generation network modes and eventually at customers’ premises.
1.5.4 MEMS:The Fourth Technology Wave
MEMS are the next logical step in the silicon revolution. We believe that the next step in the silicon revolution will be different and more important than simply packaging more transistors onto the silicon.
1.5.5 System packaging: A Fifth wave
A fifth wave, consisting of Systems Packaging that integrates and engineers all these into products (microelectronics, RF, photonics, MEMS, packaging)
1.6 Introduction to assembly and package processing
1.6.1 Packaging Hierarchy
Essentially, every electronic product contains:
(1) semiconductor devices such as ICs
(2) packaging to integrate these ICs and other devices into components
(3) system-level boards which integrate these components to form the system-level assemblies.
Level 0 – Gate-to-gate interconnections on the silicon die
Level 1 – Connections from the chip to its package
Level 2 – PCB/PWB, from component to component / to external connector
Level 3 – Connections between PCBs, including backplanes or motherboards
Level 4 – Connections between subassemblies, for example a rack
Level 5 – Connections between physically separate systems, using for example an Ethernet LAN
1.6.2 Process
1.6.3 IC Assembly and package processing
IC assembly process involves three interfaces:
(1) metallurgical bond pad interface(金属键合区) on the IC
(2) metallurgical bond pad interface on the package
*primary concerns of (1),(2): interdiffusion of metals into each other.
Effect of the diffusion on thermomechanical reliability (热机械可靠性) and electrical stability, the formation of brittle intermetallic compounds(脆性金属间化合物), volumetric change(体积变化) occurring due the formation of some intermetallic compounds (such as AuAl2), and corrosion of the bond pad metallurgy.
Possible diffusion mechanisms:
atomic diffusion where atoms jump into neighbouring vacant lattice sites; 原子扩散，原子跃迁到邻近的空晶格位
interstitial diffusion which occurs only for small atoms in the solid; 只对固体中的小原子发生的间隙扩散
interstitial pushing of an atom from its lattice site to an interstitial site; 原子从晶格位置向间隙位置的间隙推力
atomic diffusion, where two neighbouring atoms swap positions directly; 原子扩散，两个相邻的原子直接交换位置
and ring rotation of four atoms.四个原子的环旋转
(3) electrical interconnection between these two interfaces
1.6.4 Purpose and Requirements of IC Assembly
Purpose:
provide the signal and power distribution of the packaged IC to the system; 向系统提供封装IC的信号和功率分配
provide mechanical support and robustness to the fragile IC; 为易碎的集成电路提供机械支持和坚固性
provide for environmental protection of the IC.
Requirements:
provide acceptable electrical properties, including R,C,L.
provide a low-cost solution for the electrical interface between the chip and package. 为芯片和封装之间的电接口提供一种低成本的解决方案
high throughput manufacturing高通量制造. For finer pitch packaging applications, tape automated bonding provides (TAB) a low cycle time, high throughput IC assembly approach.对
high reliability. Flip chip on ceramic technology has been a highly reliable interconnection technique.
repairability or replaceability where the interconnection between the IC and package should provide for removal of a failed IC, and replacement with a new high quality IC or a new part number.
1.7 IC 组装技术（3个）need to be more specific
1.7.1 Wire Bonding
A chip-to-package interconnection technique where a fine metal wire is attached between each of the I /O pads on the chip and its associated package pin(在芯片上的每个I/O焊盘与其相关的封装引脚之间连接一根细金属线).
A fine wire—typically gold wire 25 μm in thickness—is bonded using ultrasonic bonding（超声波焊）between the IC bond pad and the matching package or substrate bond pad.
Highly flexible chip-to-package interconnection process 灵活性/工艺兼容性强
Low defect rates or high yield interconnection processing (40–1000 ppm)
Easily programmed or taught bonding cycles
High reliability interconnection structure
Very large industry infrastructure supporting the technology
Rapid advances in equipment, tools, and materials technology
Slower interconnection rates due to point-to-point processing of each wirebond
Long chip-to-package interconnection lengths, degrading electrical performance
Larger footprint required for chip to package interconnection
Potential for wire sweep during encapsulation overmolding
Aluminum metallization
Copper metallization
a metallized lead frame
a metallized chip carrier—organic laminate, polymer film, or ceramic
a metallized PCB
A. 冲切出引线框模型
B. 在引线框上合电镀键金属
C. The chip is mounted onto the lead frame or chip carrier using a die attach process
highly automated and uses high precision, high speed chip bonders
using a variety of materials including conductive epoxies and solders.
D. Fine wires are bonded between each chip I/O and the package lead frame pads or chip carrier traces
- Thermosonic and ultrasonic welding methods
E. The package is overmolded with a polymer encapsulant to provide mechanical support and environmental protection, while presenting a cooling surface for heat transfer.
Molding: a transfer molding or injection molding process
F. The packages are singulated from the lead frame carrier
G. The leads are bent to form the package leads
J lead or gull wing leads
H. The lead frame carrier or chip carrier pallet, configured in a multiple up format整齐排列
I. Next subject to functional test and burn-in testing
J. 装运
Reason: the relatively long lengths of the wires interconnecting the chip and package lead frame. This tends to increase impedance, promote inductive coupling, and slow package operating speeds.
Common failures:
Delamination of the encapsulant molding compound or die attach
Highly localized stress concentrations in the wirebonds, causing fatigue failures in the wire or bond.
A number of other failures
all forms of plastic packaging
multichip modules
hermetic packaging 气密性封装
ceramic packaging
1.7.2 Tape Automated Bonding
An IC assembly technique based on mounting and interconnecting ICs on metallized flexible polymer tapes(将IC安装和互连到柔性金属化聚合物有载带上). It is based on the fully auto-mated bonding of one end of an etched copper beam lead to an IC, and the other end of the lead to a conventional package or PWB（蚀刻铜束一端[内引线]连接到IC，另一端[外引线]连接到常规封装或PWB的全自动连接）
Ability to handle small bond pads and finer pitches on the IC
Elimination of large wire loops
Low profile interconnection structures for thin packages
Improved conduction heat transfer for thermal management
Improved electrical performance
Ability to handle high I/O counts
Ability to burn-in on tape before device commitment
Reduced weight
Basically a peripheral interconnection technique with no active circuitry under the chip bond pads
Package size tends to increase with larger I/O counts
Process inflexibility due to hard tooling requirements of the flex circuit, bond heads, etc.
Relatively little production infrastructure
Additional wafer processing steps required for bumping
Gang bonding群键合 no longer useful for the larger chips; replaced by single point thermosonic bonding
Large capital equipment investment required
Difficulty in assembly rework
Additional engineering requirements
Specialty materials and equipment requirements
Coplanarity of the beam leads with the chip and substrate
Long parallel interconnections with poor electricalperformance
System testability
A. 加工圆片凸点
B. 将圆片粘在一个弹性胶带上进行划片
C. 加工载带(多层)
D. 芯片和载带对准
E. 内引线键合(ILB)
F. 测试
G. 包封
H. 分割
I. 测试/老化
J. 引脚成型
K. 外引线键合(OLB)
Reason: short circuit lead lengths between the chip, and substrate reducing impedance and signal delays.
1.7.3 Flip Chip
an advanced form of surface mount technology, in which bare semiconductor chips are turned upside down, and hence called flip chip (i.e., active face down), and bonded directly to a printed circuit board or chip carrier substrate.
下图展示两种主流键合方法:焊料互连/电胶连接
The interconnection system can be subdivided into four functional areas:
(1)under bump metallization (UBM)
a compatible layer between the bump metallization and final chip metallization.
The structure of the UBM consists of an adhesion layer covering the chip metallization, a barrier layer, a wetting layer, and an anti-oxidation barrier
(2)chip bumps, bond materials between the bump and substrate metallization
(3)encapsulant
(4)substrate metallization.
IC键合区主要指前3部分
(1) Funtctions
A. electrical connection between the chip and the substrate
B. a heat dissipation path from the chip
C. environmental protection
D. a structural link between the chip and the substrate
(2)Types
a) Wire Stud Bump
b) Plated Stud Bump
c) Solder Bump
(3)Primary material systems
A. High temperature with melting points in excess of 250 C (examples include 95% Pb–5% Sn and 97% Pb–3% Sn)
B. Moderate temperature with melting points between 200 and 250 C (examples include 95.5% Sn–3.5% Ag–1.0% Cu, CASTIN Cu-Ag-Sb-Sn, and 85.9% Sn– 3.1% Ag–10% In–1.0% Cu, and 96.5% Sn–3.5% Ag)
C. Low temperature with melting points less then 200 C (examples include 37% Pb–63% Sn eutectic, 88% In–12% Pb, 100% In, and 48% Sn–52% In).
(4) Deposition Processes
A. Evaporation
B. Electroplating
C. Solder paste screening or printing
(1) Solder Interconnection processing
(2) Conductive Adhesive Interconnection Systems
Reason: provides the shortest possible chip-to-package interconnection distance.
in terms of minimum impedance, minimum resistance, minimum capacitance, and minimum inductance.
*MEMS Microsystems Packaging
Comparing MEMS and IC’s:
Complicated and Cost: MEMS packaging >ICs Packaging
While MEMS packaging shares many of the same objectives as IC packaging, there are important differences that make packaging for MEMS difficult. One difference is that with IC packaging, input and output signals are electrical, while the inputs to MEMS devices can be a wide variety of physical stimuli. Consequently, the packaging for MEMS devices not only needs to encapsulate the device and protect it from the environment; it must also allow the device to interact with the environment in a very limited and controlled fashion. Another difference relates to the market sizes. In the case of IC microsystems packaging, it is very common that a packaging solution can be used for a relatively large number of different IC device types thereby enabling large economies of scale and lower costs. MEMS often require customized and costly packaging solutions and thereby higher costs.
*IC assembly is the most important first step in the use of ICs.
Wire-bonding is the most used technology today, and will remain so in the foreseeable future, at least up to 700 I /Os on a single IC. For higher I /Os, flip chip or TAB are the dominant technologies.
2.1 Electrical package design, SPICE Model
Electrical package design：the process that defines the electrical signal and power paths through the package in a way that meets the overall system requirements. Ultimately, the design process is the geometrical layout of interconnects and the specification of materials.
获得满足系统要求的互连线集合版图、材料特性以及它们的几何尺寸
2.1.1 Package Functions
provide semiconductor ICs with
signal and power distribution
physical support
chemical protection against the environment
the capability to remove heat produced by the chip, to enhance the reliability of the packaging structures, and to secure the operation of the chip（否则，芯片中器件性能会随T上升而退化）
2.1.2 Electrical Functions：信号分配和功率分配
Providing signal paths between the chips, including wiring that acts as a space transformer between the chip and board to match the dimensions of the interconnections and the design of embedded passive lumped components.
Providing suitable power distribution to enable the circuits to function.
*Two aspects of electrical design: providing suitable communication paths for signals and providing suitable channels for power distribution.
The primary technical challenge for electrical design is driven by the frequency spectrum of signals.
At low frequencies, signal and power paths are easily realized since the physical geometry of the interconnects has little effect.
At higher frequencies (1 GHz and up), the realization of appropriate interconnections is much more difficult. Interconnects are physically longer than the packets of energy routed along them, and their behaviour depends on the properties of the materials and the electromagnetic fields that comprise the signal.在高频范围,互连线实际上比沿着它们走线的能量路线更长,它们的特性与互连线材料特性以及构成信号的电磁场有关。一些效应,如传输延迟、互连线结构相关的特征阻抗及寄生电抗等决定了信号的特性。因此,信号的失真度和信号到达目的地所需的时间都是互连线参数的函数。由于信号的频谱确定了芯片需要电源的速率,所以也要关心电源和地线的路径
*Parasitic Structure:
The passive components that are mounted on the package or board have equivalent circuits that define them. One example is the decoupling capacitor, which is represented as a series RLC circuit in Figure below.
2.2 Electrical Anatomy of System Packaging
2.2.1 Ohm’s Law (voltage across a resistor is V=IR)
Electrical design involves electricity: The movement of electrons in a conductor.
In packaging applications, electricity is used in both its fundamental forms: DC & AC.
Power supplied to a chip: DC
Signals in and out of the chip vary with time.
Most electrical signals are neither DC nor AC; instead, they vary with time in some nonconstant, nonsinusoidal manner. R dissipates electrical power by converting it to heat; consequently, it is usually desirable to minimize R of wires and conducting traces.
2.2.2 Skin Effect (I = C dV/ dt; V = L dI/ dt)
At DC, current flows uniformly within a conductor.
At higher frequencies, current tends to crowd along the surface of the conductors. (Skin effect)
Because of this, the AC R of conductors is considerably higher than the DC R. For AC signals, V and current sinusoids may also be out of phase with each other indicating the presence of C or L within the circuit.
2.2.3 Kirchhoff’s Voltage Laws
KVL: the voltage drops around any closed loop within the circuit must add to zero.
KCL: the sum of the individual currents into a node of the circuit must add to zero.
2.2.4 Noise
The presence of any undesired signal within a system can prevent that system from operating as intended.
2.2.5 Time Delay (time constant τ=RC and time delay τ=L/R)
The combination of R with either C or L introduces time delay into the system.
RC delay is of considerable concern to chip and package designers, 制约系统的速度
L/R delay affects the ability of an on-chip power supply.影响电源对芯片发出变化指令的瞬间响应能力，并产生SSN
2.2.6 Simultaneous Switching Noise (SSN)
the fluctuation in signals that result from a brief reduction of the local DC supply voltage at some point within the system due to the power supply’s inability to instantly respond. 由于电源不能即时响应而造成系统中某点的局部DC电源电压暂时减小引起的信号波动
One remedy to the SSN problem is to place decoupling capacitors 补偿系统中的L.
2.2.7 Transmission Lines
Although the time delays associated with electrical signals, modeled as RC and L/R delays, electricity is carried by electromagnetic waves.
Electromagnetic waves travel at the velocity of light in a particular material. In air, c=1ft/ns. For most packaging applications, it is sufficient to consider EM waves that travel in 1D. These waves can be modeled by voltages and currents on transmission lines.
2.2.8 Crosstalk
The result of a signal on one line inducing a signal on a nearby line, despite the absence of any physical connection.
Caused by parasitic R and L.
2.2.9 Electromagnetic Interference (EMI)电磁干扰
Undesired electrical effects that disrupt a system’s performance or interfere with nearby systems
2.2.10 SPICE Model
A number of general-purpose circuit analysis tools exist for simulating electronic circuits. One of these is SPICE (Simulation Program with Integrated Circuit Emphasis). This type of simulation tool contains models for all common circuit elements and many active devices, and can perform time-domain and frequency domain simulations.
In the future, the package will contain lumped passive circuit elements such as R，L，C (集总的无源电路元件).
C in the package may be used to
supply charge to the power line of the chip
isolate the inductive parasitics of bonding structures.
Lumped chip capacitors that are currently mounted on the surface or at the bottom of the package may be replaced with embedded capacitors buried inside the multi layer package.
The embedded resistors may be used for the termination of signal lines to avoid signal reflections from the ends that cause unwanted high-frequency noise and signal propagation delay.
Since the termination resistors of the signal lines determine the power consumption of the drivers, signal propagation delay and package complexity, their design can become very important.
2.3 Electrical Anatomy of System Packaging
Electrical design involves the estimation of package performance.
The electrical system specifications for the package include parameters such as delay, skew失真, loading负载, impedance阻抗, reflections反射, crosstalk串扰 and power/ground fluctuations.
To estimate the electrical performance, circuit simulation methods are often used which require the circuit models of packaging structures.
The signal lines within the package are used for the transmission of signals between chips. Based on the characteristics of the signal lines, the driver and the receiver circuitry, they can cause delay, skew and reflections, which degrade the transmitted signal.To evaluate the signal line performance, they are represented by their characteristic impedance Z0 and propagation velocity vp.
During signal transmission, the signal line can couple energy to adjacent signal lines, which results in crosstalk. Crosstalk can cause false switching of circuits and can increase delay. Crosstalk can be simulated by extracting the coupling between signal lines, such as mutual inductance Lm and mutual capacitance Cm
The chips are connected to the signal lines through bonding structures and vias. Similarly, signals exiting the package pass through pins and connectors. These structures add parasitics to the signal lines due to their R and reactance and can degrade the signal.
The passive components that are mounted on the package or board have equivalent circuits that define them. One example is the decoupling C, which is represented as a series RLC circuit
2.4 Design for reliability, Thermomechanically, Electrically and Chemically Induced Failures
2.4.1 Design for reliability
Reliable: When a product performs the functions for which it is designed.
To ensure that the electronic systems packaging will be reliable over an extended period, two approaches need to be followed:
design the systems packaging up-front for reliability
predetermine various potential failure mechanisms that could result in product failure.
create designs and select materials and processes that would minimize or eliminate the chances for failures
conduct an accelerated test on the systems packaging for reliability after the system is designed, fabricated, and assembled
subjected to accelerated test conditions for short periods of time by applying ⬆ T, ⬆ humidity, ⬆ V, ⬆ pressure, and more to accelerate the failure process
such as thermal cycling, temperature and humidity cycling and power cycling
Plastic packages are best suited for controlled environments
Ceramic packages offer the best performance in terms of thermal characteristics, moisture absorption and endurance in harsh environments.
The package must provide a good long-term reliability even in the harshest environments
The underlying cause or failure mechanism, the net result is that the system is not reliable or usable. Design for reliability aims to understand, identify and prevent such underlying failures even before the packages are built.
Methods of design against failures:
by reducing the stresses that cause the failure
by increasing the strength of the component.
2.4.2 MICROSYSTEMS FAILURES AND FAILURE MECHANISMS
Brittle脆性: hard but liable to break easily
Fragile易碎:(of an object) easily broken and damaged
Corrosion: a natural process that causes the transformation of pure metals into undesirable substances when they react with substances like water or air
Dendritic枝晶: when a metal, or an alloy of multiple metals, in liquid form freezes
Creep蠕变: a complex failure mode that describes how material deform on an atomic scale
Delamination分层: Any moisture in the material would certainly cause delamination and very expensive damage. These defects, suchas bubbles, cracks, and delaminations, are not necessarily visible, even under a microscope. Delamination tends to destroy coating strength and durability
2.4.3 Thermomechanically-Induced Failures
caused by stresses and strains (应力和应变) generated within an electronic package due to thermal loading from the environment or internal heating in service operation.
2.4.4 Design against Fatigue
Fatigue is the most common mechanism of failure and is believed to be either fully or partially responsible for 90% of all structural and electrical failures. The failure mechanism is known to occur in metals, polymers and ceramics
2.5 Design of Testability (Scan Design), Interconnection Tests (CH19.7)
Today’s ICs may contain several million/billion transistors that need to be tested to verify their gate-level functions. As the transistor count increases, the complexity of functional tests (cost of testing) also increases.
Design for testability (DFT): To reduce these cost, need to be incorporated test features into the circuit itself during the design phase.
Electrical testing: the process by which an electronic, photonic, or MEMS device, or the systems in which they are used, is guaranteed to be electrically functional before it is put to end-product use. To check if all pins have been correctly soldered. It is also about its prototyping capabilities. The two most popular DFT techniques employed are scan design and built-in self-test (BIST).
2.5.1 Scan Design
Scan circuitry greatly enhances a design’s testability, facilitates faster and improved test generation, and reduces external tester usage.
Two main types of scan circuitry: internal scan and boundary scan
2.5.1.1 Internal Scan
involves the internal modification of a design’s circuitry to increase its testability.
Scan design uses either a full or partial scan technique, depending on design criteria.
Aim: make a difficult-to-test sequential circuit behave like an easier-to-test combinational circuit.
Achieving this goal involves replacing sequential elements with scannable sequential elements (scan cells) and then stitching the scan cells together into scan registers, or scan chains. 串行
Before adding scan, the design had four inputs and two outputs. After adding scan circuitry, the design has two additional inputs, scan-in and scan-shift, and one additional output scan-out. Scan memory elements replace the original memory elements so that when shifting is enabled, scan data is read in from the scan-in line.
Operation:
Shift data into scan chains
Apply stimulus to the primary inputs
Measure primary outputs
Pulse system clock to capture new values into scan cells
Scan data out to measure the captured values while simultaneously loading new values into the scan chains
2.5.1.2 Boundary Scan (BS/JTAG)
Define: a DFT technique that facilitates the testing of PWB and MCM interconnect circuitry and the chips on those boards.
Function: detect the vast majority of board manufacturing process faults. e.g. wrong components, missing components, mis-oriented components, and components with stuck pins, shorts, and opens.
Explanation: When used on a board, BS stitches the I/O ports of the chips together into a long scan path. It associates a memory cell with each IO of a chip. These memory cells are connected serially to form a shift register. The architecture also contains a four-port standard connection, the test access port (TAP), which provides access to this shift register and controls the various chip test modes.
The test circuitry consists of the boundary scan register, a 1-bit bypass register, an instruction register, several miscellaneous registers, and the TAP.
The TAP consists of four lines
the test clock (TCK)
the test mode select (TMS)
the test data in (TDI)
the test data out (TDO) lines
Test instructions and data are sent over the TDI line. Test results and status information are sent from the chip over the TDO line. The state of the test circuitry in the chip is defined by the state transitions on the TMS line, which are decoded by the TAP controller.
Operation:
An instruction is sent serially over TDI into the instruction register.
Then the selected test circuitry is configured to respond to the instruction. This involves sending a test vector over TDI into the register selected by the instruction.
Execute the test instruction
Test results are latched into the selected register and shifted out over TDO to the external tester. Simultaneously, new data is shifted in.
Modes
The two most popular modes of BS standard based test are INTEST and EXTEST. BYPASS, IDCODE, SAMPLE, PRELOAD are some of the other test modes used.
A. EXTEST: allows testing of off-chip circuitry and board-level interconnects. Boundary scan cells at the output pins are used to apply test stimuli, while those at input pins capture test results.
B. INTEST is used to test the circuit inside a chip.
Test data shifts along the scan path, starting at TDI and ends at TDO. The scan path connects all devices on a board that contain BS circuitry.
The TDO of one chip feeds the TDI of the next, all the way around the board.
The other two inputs, TCK & TMS, connect in parallel to each boundary scan device in the scan path.
With this configuration, board interconnects can be tested, a snapshot of the normal system data is taken and individual chips are tested.
2**.5.2** Built-in Self-Test (BIST)
- Definition: a structured DFT technique that places a device’s testing function within the device itself. BIST structures can test various types of circuitry, from random logic to regular structures such as memory devices
2.6 Microsystem design for environment, traditional design
2.6.1 Traditional disign
Traditional industrial practice involves testing for reliability after the IC and the system-level packages are fabricated and assembled. If problems are found in reliability testing, the IC and the system-level packages are redesigned, refabricated, reassembled, and retested.
Cons: expensive and time consuming
Aim of design for reliability: understand and fix the reliability problems up-front in the design process, even before the IC and the system-level packages are fabricated
2.6.2 Traditional Design Flow
2.6.3 Microsystem Design for Environment
Environmental issues can be divided into the following nine categories:
Global warming
Depletion of natural resources
Ozone hole
Acid rain
Pollution of soil, subterranean sea, atmosphere and ecology
Decreasing number of rain forests
Increasing desert area
Decreasing species of wild animals
Transfer of harmful industrial waste from advanced nations to developing nations
2.6.4 LIFE-CYCLE ASSESSMENT (LCA)
The keystone to LCA is the inventory清单, consisting of the environmental influence of materials, processes, etc. These include
Raw material
Components for assembly
Energy and water
Emissions into air
Emissions into water
Waste materials for recycling or landfill
Actual product
Transport
Use of Product
Scrapping and recycling
Materials provide several functions in microelectronic packaging. They
(1)transmit signals from IC to IC
(2)supply power to ICs
(3)provide interconnections to form the system-level hierarchy
(4)mechanically and environmentally protect ICs
(5)dissipate heat. These functions are schematically depicted in Figure 3.1.
3.1 Underfill/mold compounds
The molding process aims to encapsulate the whole wire bonded die against exposure to contamination and other physical damages.
The lead frames that hold the dies are placed in individual cavities which are filled with liquid resin. (保持模具的引线框架被放置在充满液体树脂的单个腔中)
Molded Underfill: Advanced silicon package manufacturers – enabling devices that are smaller, more powerful, more robust, more affordable. But all these advancements depend on techniques – such as molded underfill, Cu pillars and stacked dies – that make package inspection much more challenging than in the past.
3.2 Solder焊料
Solders for interconnects (Sn-Pb, Sn-Ag; gold wire bonds), copper lead frames(Kovar, CuBe, Alloy 42), copper traces in substrates; Tungsten钨, molybdenum钼 traces in co-fired ceramics Layer of Tin Lead solder on the lead frame for making the PCB assembly process easier. Lead free无铅 finishing with Tin Bismuth锡铋 plating or Tin Copper锡铜 dipping can also be used.
3.3 Thermal interface materials
These are designed to help remove the heat generated by an electronic device to the ambient environment to ensure reliable operation of electronic hardware, communication equipment and portable electronics.
Thermal interface materials provide a thermal path between the heat source and heat sink. Materials are Silicon (Si) Rubber硅橡胶, Si Foam泡沫硅, Si Sponge海绵硅, Solid Si sheet固体硅片 etc.
3.4 Substrates
Three alternative chip attachments to the package substrate:
Soft Solder Die Attach: This process uses a solder material to bond the die to the lead frame. The solder is introduced as a wire preform and melted onto the hot lead frame surface as a liquid solder dot.
Epoxy Die Attach: (the most commonly used process) Usually silver-loaded polymers载银聚合物 are used, but the term generally encompasses the use of other adhesives, such as polyimide聚酰亚胺- or silicone-based materials.
Metal-filled glasses: Less used because of the high temperatures needed, but have been used in ceramic packages
3.5 Metal Alloys
- Definition: Alloys are compounds consisting of more than one metal
–Adding other metals can affect the density, strength, fracture toughness断裂韧性, plastic deformation塑性变形, electrical conductivity and environmental degradation.
–have a melting range in which the material is a mixture
of solid and liquid phases.
–Alloys can be designed with a single melting point, and these are called eutectic mixtures低熔混合物e.g. 63%Sn, 37%Pb
- Properties of Metals and Metal Alloys:
excellent thermal andelectrical conductivities
Relatively high densities, especially compared topolymers
–Materials with high densities often contain atoms with high atomic numbers, such as Au. However, some metals such as Al or Mg(magnesium) have low densities, and are used in applications that require other metallic properties but low weight.
- Fracture Toughness
– Ability to avoid fracture, especially when a flaw is introduced
- Plastic deformation
*I IC Pacakages
Packaging of an IC should provide mechanical and environmental protection of the IC, remove the heat that is generated by the IC, and provide electrical connections to the rest of the components by means of a systems-level board.
Ceramics such as alumina and glass ceramics offer good protection from the atmospheric moisture because of their hermiticity, have thermal conductivity that is high enough to help with heat dissipation and have CTE closely matching that of silicon, provides thermomechanical reliability.
Although ceramics are widely pursued by industry, they were almost completely eliminated by organic IC packages. Strongly driven by their low-cost and ease of processing, organic materials are widely used, in spite of their deficiencies when compared to ceramics. Polymers perform better electrically than ceramics because of their low dielectric constant. The materials, properties and processes for IC assembly are summarized in the first row in the above figure
*II IC Assembly
The electrical interconnections between the chip and package are provided by metal Wire bonding techniques, as indicated in the second row in the above figure. The conducting wire should have a high electrical conductivity, oxidation resistance, and good wetting to the bonding pads and mechanical properties to withstand creep and fatigue.
Al and Au are the most favoured materials for wiring because of their high electrical conductivity and corrosion resistance. Wire bonding needs any two of the three conditions that assist joining: heat, compression or ultrasonic vibration.
Wire bonding has been supplemented by TAB in instances where finer pitches are required节距较小的电气互联. TAB is a process where chips are joined to a patterned metal on polymer tape, using automated thermocompression bonding. A typical system is copper wiring on a polyimide tape. With ever-increasing input/output connections from the chip, peripheral or side-connections are being replaced by area-array interconnection packages such as a BGA, or a flip chip assembly.
*III Boards and Board assembly
System-level packaging provides wiring that forms an electrical interconnection for all components within the system. The organic substrate that provides these functions is called a PWB. MCM packages on PWB type laminates, referred to as MCM-L, limit the interconnection temperature to less than 200℃. An epoxy, reinforced with a glass cloth to provide enough stiffness, is widely used for making PWBs.
Surface mount technology (SMT) interconnections are achieved by soldering, with the most common soldering compound being an eutectic Pb-Sn alloy with a melting point of 183℃.
A huge CTE mismatch between the PWB and IC induces significant stresses that cause failure at the solder joints. This technical challenge increases with the chip size, power density and the drive to use low-cost board materials. The thermomechanical stresses that cause failure can be alleviated by using an underfill material such as epoxy, that mechanically couples the IC and substrate, hence reducing the strain on the solder.
3.6 Surface mount technology表面贴装技术
3.6.1 Wafer Preparation and Dicing
Wafers are mounted on a laminating tape that adheres to the back of the wafer. It holds the wafer throughout the dicing and the die attaching process.
The die-sawing machine using a diamond saw blade saws the wafer into the individual die/pellet on the adhesive backing tape. Deionized water and CO2 bubbles are dispensed on the wafer to remove silicon dust/debris besides lubricating(润滑) and cooling.
3.6.2 Die Attach and Wire Bonding
The die attach machine will pick up the die and deposit it on the frame. It may utilize the wafer mapping method to pick up only good die. For most processes, die attach materials like gold or lead-tin铅锡 based solder wires or silver epoxy paste 银环氧树脂膏 potting on the frame are required prior to die bonding process.
Either Au or Al wires are used depending on application. Bonded one at a time, the wire is fed through a ceramic capillary. With a good combination of temperature and ultrasonic energy，a good metalized wire bond is formed.
3.6.3 Moulding and Solder Plating
The moulding process aims to encapsulate the whole wire bonded die against exposure to contamination and other physical damages.The lead frames that hold the dies a replaced in individual cavities which are filled with liquid resin.
This step provides a layer of Tin-Lead solder on the lead frame for making easier the PCB assembly process. Lead free finishing with Tin Bismuth plating or Tin Copper dipping can also be used.
3.6.4 Marking and Lead/Form
Marking is the coding process that writes customer’s corporate and product identification code on a packaged device. It commonly uses a laser-based machine
The final process is to trim away 修剪 the leads of the packaged device from the frame strip.The leads are cut and formed mechanically to the specified shape
3.7 Chip-Package Connection
3.7.1 Wire Bonding
- Connections are made from the chip to the pad frame via thin wires
–Typically 100*100 um metal pads on 200 um pitch
–Mechanical bonding of one pin at a time(sequential)
- The wires are made of low R alloys / doped metals
–Gold and Al
–Also copper and silver
–Typically 25um diameter for logic devices
3.7.2 TAB
- Tape automated bonding
–The interconnections are patterned on a multilayer polymer tape.
–The tape is positioned above the ‘bare die’ so that the metal tracks (on the polymer tape) correspond to the bonding sites on the die
–After the chip leads are cut and soldered to the board, the chip is covered with a glob of epoxy or plastic
A bare chip that is mounted directly onto the PCB. After the wires are attached, a glob of epoxy or plastic is used to cover the chip and its connections. The TAB process is used to place the chip on the board.
This side view shows how the wires connect the chip to the PCB
- Pros over wire bonding
–Smaller and closer pads.
–higher density, up to 850 pins
–Better electrical characteristics
–Faster procedure but more expensive machinery
3.7.3 Flip-Chip
The chip is “soldered” to the package substrate using the solder balls “bumps” that have been grown over the die pads
Pros:
Lower cost than wire bonding since the bumping was done at wafer level and since all connections are made simultaneously
Higher reliability than wirebonding and beam lead bonding
Better electrical performance than wirebonding due to its lower R, C, L
Reparability: If an IC was defective, either during assembly or during usage, it can be removed and a new IC is flip chip bonded on the same ceramic substrate.
Improved chip designs may be substituted on multichip modules.
Cons:
Flip Chip Defects and Failure Modes: Bulk Underfill Cracking, Solder Fatigue Cracking, Fillet Cracking, Center Die Cracks, Edge Cracking, Die Cracking, Delamination/Void Growth, solder migration.
倒装芯片缺陷和失效模式:大块下填充裂纹、焊料疲劳裂纹、圆角裂纹、模具中心裂纹、边缘裂纹、模具裂纹、分层/空洞生长、焊料迁移。
3.8 Packaging Materials and Properties
3.8.1 Electrical Properties: Conductivity
When an electric field is applied onto a conductor, the electrons drift towards the positive potential, resulting in a current. Electrical conductivity is the ratio of current density and the applied electric field
J=σE
where J is the current density [A/m2], σ is the electrical conductivity [Ohm-1m-1] and E is the electric field [V/m]. σ is a measure of the number of available electrons for conduction and their mobility. The inverse of electrical conductivity is resistivity. Electrical conductivity depends on the material and temperature.
3.8.2 Thermal Properties: Thermal Conductivity:
The amount of heat transferred through a material per unit of time, denoted as heat flux Q, is proportional to the temperature gradient (dT/dx). The ratio of heat flux and temperature gradient is termed thermal conductivity:
Q_x/A=−K_xdt/dx
A is the area of conduction medium and x is the direction of heat flow. It is expressed as W/mK.
Heat flows from a high temperature to low temperature region, and therefore, a minus sign in the above equation makes the conductivity a positive number. Thermal conductivity is a very important property for dissipation of heat from an IC. The heat evolution from an IC may range from 1 watt for portable products to as much as 150 watts per chip for high-performance computer applications. The thermal conductivity is a measure of the ease with which heat can flow through a material. High thermal conductivity materials allow for easy heat dissipation from the chip, and hence, control the chip temperature.
*Definitions
Resin: a generic term used to designate the polymer, polymer precursor material, and/or mixture or formulation thereof with various additives or chemically reactive components. 树脂:用于指聚合物、聚合物前体材料和/或其与各种添加剂或化学反应组分的混合物或配方的通称。
Molding: the process of duplicating topographic information in a functional material by solidifying its liquid precursor molecules on a master.通过将液态前体分子固化在母材上来复制功能材料的地形信息的过程
Molding is a forming process using molds. Materials such as synthetic resins (plastics) are heated and melted, and then sent to the mold where they are cooled to form the designed shape. Due to the resemblance to the process of injecting fluids using a syringe, this process is called injection molding.成型是利用模具进行成型的过程。合成树脂(塑料)等材料被加热和熔化，然后送到模具中冷却，形成设计的形状。由于类似于用注射器注射液体的过程，这个过程被称为注射成型。
4.1 Definition of Microelectronics, and the characteristics of Semiconductor
4.1.1 Introduction
ICs, based on microelectronic devices, form the basis of all modern electronic products. Continuous advances in reducing the size of the transistors allowed the progressive integration of tens, hundreds, then thousands of transistors on a single IC in technologies called small, medium, and large scale integration (SSI, MSI, and LSI). This led to the integration of up to a million transistors on an IC, called very large or ultra scale integration (VLSI or ULSI).
4.1.2 the characteristics of Semiconductor
Semiconductors have four valence electrons, which require a moderate amount of external energy in order to be removed.
The valence shell of an atom represents a band of energy levels and the valence electrons are confined to that band. When an electron acquires enough additional energy from an external source, it can leave the valence shell and become a free electron and exist is what is known as the conduction band.
4.1.3 Semiconductor Devices
MOSFET
CMOS
4.1.4 IC and SOC
IC Definition: The semiconductor materials constitute the devices, and the devices are interconnected to form functional circuits. An integration of many such circuits or components on a single chip is called an integrated circuit (IC).
SoC Definition: a concept where electrical, optical, mechanical, chemical, and biological devices will be integrated together on a single chip.
Figure 4.10 shows a personal handy phone system design by the SOC concept, where various components shown in the figure are integrated on a single chip.
4.1.5 Types of IC
ICs are roughly divided into two categories: (1) hybrid and (2) semiconductor
(1)A hybrid IC (HIC) contains interconnected diodes, capacitors and resistors fabricated on a single plastic, ceramic or insulated aluminium substrate and has the capability of performing a complete electronic circuit function. It is called hybrid since it involves two or more material types.
(2)Semiconductor ICs only contain devices fabricated from semiconductor materials.
4.2 IC Packaging and challenges
4.2.1 Intro
The electronic packages are to protect, power, and cool the microelectronic chips and provide electrical and mechanical connection between the microelectronic part and the outside world. Whether a single transistor or a GSI chip, they have to be packaged.
芯片到系统工艺步骤
4.2.2 Different Types of IC Packaging
Many types of IC package technologies have been developed that vary in their structures, materials, fabrication methodology, bonding technologies, size, thickness, number of I /O connections, heat removal capability, electrical performance, reliability, and cost.
In general, IC packages can be classified into two categories: 1) through-hole, and 2) surface mount.
4.2.3 IC Packaging Challenges
- Reason:
(a)the on-chip silicon system can out-perform the speed capability of the package.
(b)as volume production techniques continue to drive the cost of bare silicon chips down, the cost of the packaging constitutes a greater and greater proportion of the total system cost. 封装成本所占比例增大
For both of these reasons, the challenges for future electronic packages are becoming extremely complex and the demand for microelectronics packaging engineers is growing.
These challenges of high performance and low-cost packages must be resolved by microelectronics packaging engineers and systems integration engineers. In order to find effective solutions to these problems, the engineers must acquire a solid educational background in multidisciplinary areas. These areas include electrical, mechanical, and thermal design, fabrication of systems based on materials (metals, ceramics, polymers), material interface challenges, testing, assembly, and package reliability.
4.3 Semiconductor Roadmap
4.3.1 The international Technology Roadmap for Semiconductors (ITRS)
Updated every two years by a group of semiconductor companies known as the Semiconductor Industry Association (SIA)
Projects the technology requirements for six different product categories up to 10–15 years ahead
These product categories are low-cost, hand-held, cost/performance, high performance, memory, and harsh environment.
4.3.2 Most Important IC Packaging Parameters
(1) I/O引脚数目
原因：controls the pitch of the IC package as well as the wiring needs at the system level.
(2) size of the IC
原因：controls the reliability of the IC to package connection.
(3) power
原因：controls heat dissipation properties of IC and system-level packaging.
*Why Silicon?
Silicon is the most widely used semiconductor material in microelectronics because of its material properties, and also because it can easily be extracted from naturally abundant silica (SiO2). The Si atom consists of a nucleus with 14 electrons revolving around it in a system, which may be compared to the sun and its planets moving in their orbits. Electrons have negative charge, and the Si nucleus has a positive charge, which offsets the charge on these 14 electrons, so the Si atom is electrically neutral. The electrons move in orbits around the nucleus. An atom which has eight electrons in its outermost orbit, or the outermost shell, is relatively stable, which it acquires by sharing one from each of four adjacent atoms in covalent bonds. Silicon has four electrons in its outermost shell, and it requires four additional electrons to become stable. Silicon can be easily doped to increase its electrical conductivity to create N-type or P-type material, which is then used to make various microelectronic devices.
5.1 Anatomy of a Microsystem
Most of the microsystems can be classified into six categories: automotive, computer and business equipment, communications, consumer, industrial and medical, military and aerospace. The total market is illustrated in figure 5.1
The pyramidal hierarchy spans from minerals to materials, processing these materials into ICs, devices and components, and electrically and mechanically designing, testing and assembling these components onto system-level boards as illustrated in Figure 5.2.
Electronic components can be roughly characterized into active and passive components.
Active components consume power in delivering functionality within a system
Passives provide connection, mechanical support, filtering, noise reduction, and other functions.
5.2 Role of Packaging in the Computer Industry
Microelectronics and computers are virtually synonymous. By the time electronic devices migrated from vacuum tubes to discrete transistors and finally to integrated circuits, the digital computer became the driving force for almost all new semiconductor-related technologies.
Microelectronics being challenged by network and portable communications products, where the need for low power, high performance and integration of passive components are becoming important.
Some important parameters are described below:
Bandwidth Is the Most Important Parameter in Computing
How Do Computers Work?
Computer System Performance
How Does Packaging Affect System Performance?
How Does Microsystem Packaging Affect the Bus Design?
5.2.1 Bandwidth –determines the computer’s performance
Definition: the number of parallel datum bits (the width) delivered to destination multiplied by delivery frequency in digital systems. The units of bandwidth are bits per second (b/s).
e.g., a 64 bit bus that uses a 100 MHz clock frequency but uses the up and down clock transitions to introduce data onto the bus is said to transmit 12.8 Gb/ s. In terms of bytes (eight bits to a byte) transmitted, it is a 1.6 GB/ s bus.
5.2.2 How Do Computer Work?
In the diagram, the data to be processed enters the computer through the input/output (I/O) subsystem. Data is moved through the memory cache hierarchy (L2 and L1) and delivered to the μP for processing.
The bandwidths of the various interconnection buses used determine the total amount of data that is moved between the levels of memory and the μP is. Bandwidth is important to packaging engineers because it is their contribution to the overall system performance.
5.2.3 Computer System Performance
Computer system performance is a function of many different variables. A very simple expression for performance is:
Perf (performance) = (μP Speed) (MIPS/MHz) (μP Utilization)
Performance (Perf) is commonly stated in terms of MIPS or millions of instructions per second. As expected, MIPS are directly proportional to the μP speed (in MHz).
5.2.4 How Does Packaging Affect System Performance?
Microsystems packaging is the enabler for good bus performance. A good bus has to be very fast and very wide. It is important for the connection between the μP and the L2 to run at the μP ’s speed and deliver at least one cache word (8B for an Intel@Pentium) per cycle with no more delay than one cycle time. This will minimize the μP wait states caused by an L1 cache miss, need for a fast bus
5.2.5 How Does Microsystems Packaging Affect Bus Design?
Package speed is important for high-performance bus design. Package attributes that support high speed are:
High via and wiring densities for shorter line lengths
Low dielectric constant materials for high propagation speed and low capacitance.
A large count of vias in conjunction with thin dielectric layers and many power planes to support low noise and good power distribution
5.3 Role of Packaging in Telecommunication Industry
5.3.1 The Communication Industry
Communications is the act of exchanging information. This exchange is done by dozens of different products that make up the second largest electronic and most technologically exciting industry.
5.3.2 Multimedia Arrives at Forefront
It refers to the combination of multiple types of content into the same message and into the same transmission medium, each type of content has different requirements for performance and service reliability.
e.g., voice content is delay-sensitive, but data content, which is not delay sensitive, but a single missing or wrong bit will render the entire message useless.
5.3.3 Bandwidth Is the Main Problem in Communications:
The problem with mobile phones and other means of wireless communications is the very limited bandwidth. This is where photonics comes into play. It is best if that phone function is packaged as a fully integrated microsystem, either with emerging system-on-package (SOP), system-on-chip (SOC) technology or both.
5.3.4 Battery and Weight:
Battery: Requirement is the life of the battery. It is necessary to design the circuits so that the life of the battery is maximized.
Weight: One of the main system requirements is low weight of the unit, number of ICs and system level board.
5.4 Role of Packaging in Automotive Systems
5.4.1 Market Size
approximately the same size as the electronics industry.
5.4.2 Electronics Content
In general, an automotive subsystem with an electronic content, such as an airbag deployment system, Sensors are included, but vehicle lighting is not.
Cost, size and weight reductions are also major factors that influence packaging of automotive electronics products.
5.4.3 Characteristics of Automotive is Harsh Environment
Automotive electronics presents some of the biggest challenges in system packaging. For example, under the hood the temperature in a car can be as low as 40℃, and 204℃ somewhere in the world.
At present, automotive electronic modules are designed for an operating temperature of 125℃. Technology advances in thermal management will help these challenges.
5.4.4 Electronic Packaging Technologies
IC and System Substrates Technologies (Substrates can be classified as Organic, Ceramic, and plastic)
5.4 Role of Packaging in Medical Electronics
5.4.1 Implantable Electromedical Devices
There are several electronic devices used in the human body to regulate, monitor or enhance bodily functions, and thus enhance the quality of life of all ages. The devices are hearing aids and heart pacemakers (Implanted Pulse Generator) etc.
5.4.2 Medical Systems Packaging Has to Be Ultra-reliable
The requirements of these medical devices are focused on reliability, size, functionality and longevity.
5.4.3 Medical Systems Packaging Has to Be Ultra-compact:
The classic problem faced by the packaging engineer is finding a way to incorporate increasing functionality and performance into a smaller and less intrusive volume for the patients.
5.4.4 Microsystems Play a Dominant Role in Medical Electronics
e.g.,The functions of a representative cardiac device include:
Sensing the heart’s electrical activity
Sensing the motions and activity level of the patient
Sensing the blood flow to and from the heart
Determining the required pacing algorithm from the sensed data.
……
These functions require very low-voltage microprocessors, mixed-signal ASICs, analog, digital-to-analog and analog-to-digital converters, high-bandwidth telemetry, high-power diodes, protection circuits, long-lived batteries and high-voltage capacitors, all interconnected together in a hermetically-sealed titanium case.
5.6 Role of Packaging in Micro-Electro-Mechanical Systems (MEMS) Products
5.6.1 Benefits of MEMS
The influence of MEMS is made possible through their benefits in cost, functionality, size, and reliability.
5.6.2 MEMS in Microsystems
Dozens of applications exist for MEMS.
e.g.The ink jet uses a MEMS chip that rapidly propels droplets when an electrical impulse is received.
The chip consists of microscopic jet nozzles that discharge droplets using piezoelectric or thermomechanical pumps inside the chip. The numerous micronozzles must be kept clean and yet it has to be packaged and protected. This can be done by selective packaging.
Hermetic packaging works well but it is expensive.
One concept is cap-on-chip illustrated in the following pic.
A silicon, metal or ceramic cap is bonded over the active area of MEMS chip while leaving wirebonds pads clear The capping must be done under cleanroom conditions in a vacuum, and the wafer is then singulated and the chips bonded and overmolded.
5.6.3 MEMS Play a Major Role in Medical Electronics
MEMS are already an important part of the medical electronics markets. Soon, MEMS will go further to enable remote diagnostics and patient independence.
e.g., The micropump is a system in which a flow sensor measures the pumping rate and adjusts it accordingly to provide measured doses or correct dose of medication.
5.6.4 MEMS Applications
MEMS accelerometers are currently used in industrial process control systems. Industrial MEMS accelerometers are applied in the measurement of gravity to determine orientation tilt and inclination; inertial measurement of velocity and position for motion control; and vibration and shock measurement for machine reliability.
6.1 Introduction to Si processing
Technology for (Si) wafer fabrication applications:
CMOS electronic industry (ICs)
Micro-Electro-Mechanical Systems (MEMS)
Micro-Opto-Electro-Mechanical Systems (MOEMS)
Radiation/particle detectors
Si technology is very much interested in photonics for solving its interconnect bottleneck problem if and only if photonic solutions are provided on Si platform
Photonics technology needs integration for continuing its growth. Si is the most mature technology for integration
6.1.1 MEMS and Microsystems
MEMS: the integration of mechanical elementssensors, actuators,and electronics on a common silicon substrate throughmicrofabrication technology
Microsystems: Engineering systems that could contain MEMS components that are design to performspecific engineering functions
The MEMS revolution harnesses ICs know-how to build working microsystems from micromechanical and microelectronic elements.
MEMS is a multidisciplinary field involving challenges and opportunities for electrical, mechanical, chemical, and biomedical engineering as well as physics, biology, and chemistry.
As MEMS begin to permeate more and more industrial procedures, society as a whole will be strongly affected because MEMS provide a new design technology that could rival—perhaps surpass—the societal impact of integrated circuits.
6.1.2 MEMS 封装方法
- 陶瓷封装
e.g. Packaging of MEMS comb-drive relays in a PGA ceramic package
塑料封装
金属封装
6.1.3 Si Processing
6.1.4 Si Photonics
- Future Packaging Si Photonics
Photonic crystals, also known as photonic bandgap materials, are periodic nanostructures. Photonic crystal basics is the periodic arrangements of two materials with different index of refraction.
Figure: Illustration showing data center connections. The shorter server-to-server connections within the server rack typically require <5m (green) of routing, longer connections between the server racks may require up to 500m (orange), and long span connections within a building or between buildings can measure up to 2km (blue).
A “leaf” is typically the top-of-rack (ToR) switch that links to all servers within a common tower or rack. The next layer of switches is represented by the “spine.” The spine is a higher capacity switch (40 or 100 GB per link) that connects to leaf switches (across the server racks), to other spine switches, and to the next level of “Core” switches. “叶子”通常是连接到公共塔或机架内的所有服务器的机架顶部(ToR)交换机。下一层交换机由“主干”表示。主干交换机是一个更高容量的交换机(每条链路40或100千兆字节)，它连接到叶交换机(跨服务器机架)、其他主干交换机和下一级“核心”交换机。
- Advanced Packaging with Si Photonic Die
Figure: Silicon photonic
a) a photonic integrated circuit (PIC) with flip-chip mounted laser die and edge-coupled waveguide; 采用倒装激光芯片和边缘耦合波导的光子集成电路(PIC);
b) logic, HMC(混合内存立方体,一种高性能内存) and PIC(光子集成电路) mounted directly to a BGA(Ball Grid Array，球栅阵列) substrate;
c) logic and HBM mounted on a high-density interposer with copper pillar micro-bumps that enable high-speed connectivity; 逻辑组件和高带宽内存（HBM）安装在具有铜柱微凸点的高密度中间层上，以实现高速连接
d) cut-away revealing copper pillar, flip-chip, BGA and optoelectronic interconnections. 剖开露出铜柱、倒装芯片、BGA和光电子互连。
- Silicon photonics market forecast
Figure: Silicon photonics growth rates will initially be dominated by applications within the data center. The data center need for speed and capacity.
6.2 Development of interconnects and impact on IMAX (Interconnection Maximum?)
6.2.1 System Interconnection
6.2.2 Silicon Interposers
An interposer can be defined as a silicon chip that can be used as a bridge or a conduit that allows electrical signals to pass through it and onto another element. Interposers are normally very frequently used in multi die chips or boards. 中间体可以定义为一个硅芯片，它可以用作桥或导管，使电信号通过它并进入另一个元件。中间体通常非常频繁地用于多模芯片或电路板。
6.2.3 Through-Silicon Vias (TSV)
If the processor die is placed on the top, TSV requirements in both counts and size would cause significant mechanical concerns (e.g., crack, stress) for the memory dice at the bottom.
6.3 Low-k Intralayer Dielectric (ILD) and its impact on electronic assembly and packaging
The use of low κ materials as the final intralayer dielectric (ILD) layer can impact the integrity of edge seals, blown fuses, and even the interface integrity at lower levels. 使用低κ材料作为最终的层内介电层(ILD)层会影响边缘密封、熔断保险丝的完整性，甚至影响较低水平的界面完整性。
Furthermore, the influence of the final ILD on lower levels depends on the total number of metal levels in the product. This paper?? addresses the role of final ILD in both environmental and package reliability, and the use of predictive modeling of mechanical reliability.
As described earlier, the use of low-κ ILD to reduce on-chip interconnect parasitic capacitance has exacerbated the difficulty of maintaining high thermomechanical reliability of die assembled on organic substrates in flip chip packages.
Due to the fragile nature of low-κ ILDs in the die and their relatively poor adhesion to the surrounding materials, it is becoming progressively critical to minimize stresses imparted on the chip during thermal cycling and wafer-level probing.
The large CTE(“Coefficient of Thermal Expansion”，即热膨胀系数) mismatch between the silicon die (3 ppm/°C) and the organic substrate (17 ppm/°C) have been shown to be destructive for ILD materials and their interfaces.
6.4 Impact of die thinning on electronic assembly and packaging.
6.4.1 Benefits of Thinning
Reducing thermal resistance
Improving device performance
Increasing reliability
Lowering overall package height
Minimizing die stress, which occurs due to mismatches in the coefficient of thermal expansion (CTE) between the silicon die and the board materials
6.4.2 Die Packaging
Definition: embedded die packaging, the idea is to embed components inside the substrate using a multi-step manufacturing process. Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. [embed – to envelope, to enclose]
6.4.3 Die or Wafer Thinning Process(Part of Die Prep)
The Die Prep process essentially involves multiple steps and encompasses wafer thinning (backgrinding), wafer singulation and pick & place in a nut-shell.
Optimum Die Prep process not only ensures quality of the dies but also helps to lower the cost and also prevents unexpected assembly hiccups.
Wafer backgrinding is a process of removing material from the backside of a wafer to a desired final target thickness while active devices are already fabricated on the wafer front side.
6.4.4 Chip Attachment to the Package Substrate
- The die attachment compound should provide
– Electrical grounding
– Thermal dissipation
- There are three alternatives
– Soft Solder Die Attach: This process uses a solder material to bond the die to the lead frame. The solder is introduced as a wire preform and melted onto the hot lead frame surface as a liquid solder dot.
– Epoxy Die Attach: Epoxy die attach is the most commonly used process. Usually silver-loaded polymers are used, but the term generally encompasses the use of other adhesives, such as polyimide- or silicone-based materials.
– Metal-filled glasses: Less used because of the high temperatures
needed, but have been used in ceramic packages
6.5 Integrated Circuit Packaging
- Classification
SSI (Small-Scale Integration) – few transistors
MSI (Medium-Scale Integration) – hundreds
LSI (Large-Scale Integration) – thousands
VLSI (Very Large-Scale Integration) – millions
ULSI (Ultra Large-Scale Integration)
- IC package engineering assembly services include:
Die attach
Ultra-fine pitch wire bond (Al & Au)
Flip Chip
Encapsulation and transfer mold
Substrate solder ball attach
Device Singulation
- Methods of interconnections
In electronics manufacturing, IC packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a “package”, supports the electrical contacts which connect the device to a circuit board.
Wire bonding: the method of making interconnections between an IC or other semiconductor device and its packaging during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC to other electronics or to connect from one PCB to another
Thermosonic bonding is widely used to wire bond silicon integrated circuits into computers.
6.6 Mechanical and Thermal
The IC package must resist physical breakage, keep out moisture, and also provide effective heat dissipation from the chip. Moreover, for RF applications, the package is commonly required to shield electromagnetic interference, that may either degrade the circuit performance or adversely affect neighbouring circuits.
Finally, the package must permit interconnecting the chip to a PCB. The materials of the package are either plastic (thermoset热固性 or thermoplastic热塑性), metal (commonly Kovar) or ceramic.
For top side heat flow path, potential thermal management options.:
a) use of higher conductive molding compound
b) embedded heat spreaders
c) improved package to casing thermal interface material
For bottom side, i.e. board side, heat flow path, thermal performance enhancement options include:
a) use of thermally conductive under-fill between package and board
b) dummy solder balls between package and board
c) embedded heat spreader within the package substrate
d) high conductive die attach between die and die to substrate.
System Level enhancement options include use of thermally conductive enclosure, venting grill, and active moving device close to the device
The thermal cycles and specific use cases for many consumer products impose mechanical stresses that require test to ensure reliability of the products.
The “drop test” approaches that have been used for cell phones and some other consumer products need to be replaced by new approaches that test a wider range of stresses including those associated with the thermal cycles experienced in the use cases.
In addition, we need tests that fit in a production flow without excessive test time or test cost. This remains a challenge not yet met.
*SIP(System in Package ) structures
Definition: a combination of multiple active electronic components of different functionality, assembled in a single unit, which provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components, and other packages and devices.
Quad flat packages (QFP)
7.1 Basic concepts in thermal analysis and thermal design
7.1.1 Thermal Management
The resistance to the flow of electrical current through the leads, poly-silicon layers, and transistors comprising a semiconductor device, results in significant internal heat generation within an operating microelectronic component.
In the absence of cooling(heat removal mechanisms), the temperature of such an operating component would rise at a constant rate until it reaches a value at which the electronic operation of the device ceases or the component loses its physical integrity.
Placing the device in contact with a lower temperature solid or fluid, facilitates heat flow away from the component. Due to this cooling, the temperature rise is moderated as it asymptotically approaches an acceptable steady-state value. Thermal conduction, convection, and radiation, as well as phase change processes, all play a role in electronics cooling.
Despite the wide variety in size, power dissipation, and sensitivity to temperature, the thermal management of all microelectronic components is motivated by similar concerns and a common hierarchy of design considerations.
Primary and foremost aim of electronic thermal control: The prevention of catastrophic failure (an immediate and total loss of electronic function and package integrity)
An understanding of the catastrophic vulnerability of the specified component(s) makes it possible to select the appropriate fluid, heat transfer mode, and inlet coolant temperature, and thus establish the required thermal control strategy early in the design process.
7.1.2 Packaging Levels and Heat Removal
The commonly accepted categorization places the chip package, which houses and protects the chip, at the bottom of the packaging hierarchy (level 1)
The PWB, which provides the means for chip-to-chip communication, constitutes level 2
The backplane or ‘‘motherboard,’’ which interconnects the printed wiring boards, is termed level 3 packaging.
The box, rack, or cabinet which houses the entire system is generally referred to as level 4
7.2 Thermal Management Fundamentals
In order to determine the T differences encountered in the flow of heat within electronic systems, it is necessary to recognize the relevant heat transfer mechanisms and their governing relations.
In a typical system, heat removal from the active regions of the microcircuit(s) or chip(s) may require the use of several mechanisms, some operating in series and others in parallel, to transport the heat generated by the chip to the coolant or ultimate heat sink.
In electronic cooling, it is generally necessary to deal with three basic thermal transport modes: conduction (including contact resistance), convection, and radiation.
7.2.1 1-D Conduction
The flow of heat from a region of higher T to a region of lower T within a solid, stationary liquid, or static gaseous medium(固体、静止液体或静止气体介质), as depicted in Figure, is termed conduction heat transfer, and occurs as a result of direct energy exchange among molecules. Conduction is governed by the Fourier equation, which in one-dimensional form, is expressed as:
$$q=-kA\frac{dT}{dx}$$ (6.1)
where q is the heat flow (W), k is the thermal conductivity (W/mK), A is the cross-sectional area for heat flow (m^2), and dT/dx is the temperature gradient in the direction of heat flow (K/m).
Integration of Equation (6.1) will yield the temperature difference resulting from the steady conduction of heat across a distance, L, through a medium, as:
$$T_{1}-T_{2}=\frac{qL}{kA}$$ (6.2)
7.2.2 Heat Flow across Solid Interfaces
Heat transfer across an interface, formed by the joining of two solids, is usually accompanied by a measurable T difference, which can be associated with a contact or interface resistance.
For perfectly adhering solids, geometrical differences in the crystal structure (lattice mismatch) can impede the flow of phonons and electrons across the interface.
However, when real surfaces are abutted, as shown in Figure, asperities on each of the surfaces limit actual contact between the two solids to a very small fraction of the apparent interface area. As a consequence, the flow of heat across such an interface involves solid-to-solid conduction in the area of actual contact, Ac, and fluid conduction across the open spaces, Av. At elevated T or in vacuum, radiation heat transfer across the open spaces may also play an important role.
If each of the solids has surface irregularities of average height δ/ 2, heat flows across the interface in two parallel paths, that is, through the solids and through the fluid. The heat flow across the interface can be written as:
$$\color{bleck}{q=\frac{T_1-T_2}{\delta/(2k_1A_c)+\delta/(2k_2A_c)}+\frac{T_1-T_2}{\delta/(k_fA_v)}}$$ (6.3)
where k1 and k2 are the thermal conductivities of solid blocks 1 and 2, respectively, and kƒ is the conductivity of the fluid occupying the gap between the two solids.
Equation (6.3) reveals that the contact area, asperity height, and the thermal conductivities of the media forming the interface all play important roles in establishing the interfacial heat transfer rate.
7.2.3 Heat Flow from Solid to Fluid: Convection
The transfer of heat from a solid to a fluid in motion occurs by a mode termed convection, as depicted in Figure.
Heat transfer by convection includes two mechanisms:
exchange among nearly stationary molecules adjacent to the solid surface, as occurs in heat conduction
the transport of heat away from the solid surfaces by the bulk motion of the fluid.
Newton’s Law of Cooling: Convective heat transfer presumes a linear dependence of heat flow on the temperature difference between the surface and fluid.
$$q=hA(T_{s}-T_{f})$$ (6.4)
where h (W/m^2* K) is the heat transfer coefficient, A is the wetted surface area, Ts is the surface temperature and Tƒ is the bulk temperature of the nearby fluid.
7.2.4 Thermal Radiation
Radiation heat transfer occurs as a result of the emission and absorption of the energy contained in electromagnetic waves or photons. Thermal radiation can occur across a vacuum or any medium that is transparent to infrared wavelengths (typically larger than 1 μm). Thermal radiation is governed by the difference between the source and sink T raised to the fourth power, as:
$$Q=\varepsilon \sigma A(T_1^4-T_2^4) F_{12}$$ (6.5)
where 𝜀 is the emissivity, 𝞼 is the Stefan-Boltzmann constant, equal to 5.67 *10^-8 W/m^2K^4 and F12 is the so-called radiation ‘‘view factor’’ between surfaces 1 and 2. For highly-absorbing and emitting surfaces placed in close proximity to each other, F12 is close to unity.
For modest temperature differences, Equation (6.5) can be linearized to the form:
$$\color{black}{\mathrm{Q=h_rA~(T_1-T_2)}}$$ (6.6)
where hr is the effective radiation heat transfer coefficient, and is approximately equal to:
$$\color{black}{\mathrm{h_r=4\varepsilon\sigmaF_{12}(T_1T_2)^{3/2}}}$$ (6.7)
7.2.5 *Lumped Capacity Heating and Cooling
For an internally-heated solid of relatively high thermal conductivity, which is experiencing no external cooling, the temperature will undergo a constant rise rate, according to:
$$\frac{dT}{dt}=\frac{q}{mC_{\rm p}}$$ (6.9)
q (heat flow): the rate of internal heating (W)
m: the mass of the solid (kg)
Cp: the specific heat of the solid (J/ kgK)
When this same solid is externally-cooled, the temperature rises asymptotically towards the steady state temperature.
$$T(t)=T(0)+\bigtriangleup T_{\rm ss}(1-e^{-\frac{hAt}{mC_{\rm p}}})$$ (6.10)
- $$\bigtriangleup T_{\rm ss}$$: the steady-state temperature determined by the convection relation (Equation 6.4).
Heat flow from such a convectively-cooled solid to the surrounding fluid encounters two resistances: a conduction resistance within the solid and a convection resistance at the external surface.
When the internal resistance $$\ll $$ the external resistance, the temperature variations within the solid may be neglected and the lumped capacity solution may be used.
The Biot Number, Bi, can be used to determine the suitability of this assumption:
$$Bi=\frac{\rm Internal~ Conduction~ Resistance}{\rm External Surface Convection ~Resistance}=\frac{(\frac{L}{kA})}{\frac{1}{hA}}=\frac{hL}{k}$$ (6.11)
h: the heat transfer coefficient at the external surface
k: thermal conductivity of the solid
L: the characteristic dimension is defined by volume of the object per unit external surface area.
For Bi 0.1, it is generally acceptable to determine the solid temperature with the lumped capacity approximation.
7.2.6 Thermal Resistances
- Thermal ‘‘Ohm’s Law’’
The temperature-difference form of Fourier’s Law, Equation (6.2), it is possible to define a thermal resistance (_R_th), as:
$$R_{th}=\frac{\bigtriangleup T}{q}=\theta_{ja}=\frac{T_{j}-T_{a}}$$ (6.12)
Tj: the junction temperature in ℃
Ta: the ambient temperature in ℃
_q：_the power of the component
Strictly speaking, this analogy applies only to conduction heat transfer, it is
possible to generalize this definition to cover all forms of thermal transport
As a first approximation, the package’s total thermal resistance can be separated into two components: $$\theta _{jc}$$—depending on the internal construction of the package and largely due to thermal conduction; and $$\theta _{ca}$$—depending on mounting and cooling techniques and due largely to thermal convection.
Conduction: $$R_{th}=\frac{L}{kA}=\frac{1}{k(\frac{A}{L})}=\frac{1}{kS}$$ S:conduction shape factor
Convection: $$R_{th}=\frac{1}{hA}$$
- Interface Resistances
Based on $$\color{bleck}{q=\frac{T_1-T_2}{\delta/(2k_1A_c)+\delta/(2k_2A_c)}+\frac{T_1-T_2}{\delta/(k_fA_v)}}$$, the interfacial heat flow is related to the separation gap between the two surfaces.
The pressure imposed across the interface and the surface hardness, as well as the surface roughness characteristics of the solids, determine the interfacial gap, $$\delta$$, and the contact area, Ac.
the area-weighted interfacial gap, Y:
$$Y=1.185\sigma\left[-\ln\left(\frac{3.132P}H\right)\right]^{0.547}$$ (6.18)
$$\sigma$$: the effective RMS surface roughness, $$(\sigma_1^2+\sigma_2^2)^{0.5}$$(m)
P : the contact pressure (Pa)
H : the surface hardness (Pa).
*Please note that $$\sigma$$ in Equation (6.18) is different from the Stefan-Boltzmann constant introduced for the determination of radiation heat transfer earlier in this chapter.
So, $$R_{\mathrm{int}} = \left[ 1.25k_s \left(\frac{m}{\sigma}\right)\left(\frac{P}{H}\right)^{0.95} + \frac{k_g}{Y}\right]^{-1}$$ (6.19)
m: the effective RMS absolute surface slope $$(m_1^2+m_2^2)^{0.5}$$
ks: the harmonic mean thermal conductivity, defined as $$\frac{2k_{1}k_{2}}{k_{1}+k_{2}}$$.
- Thermal Resistances in Series
$$R_t=R_1+R_2+R_3+R_4=\frac{L_1}{k_1A}+\frac{L_2}{k_2A}+\frac{L_3}{k_3A}+\frac1{hA}$$ (6.20)
The wall temperature _T_1: $$T_1 = R_tq+T_a$$ (6.21)
- Thermal Resistances in Parallel
$$\frac1{R_t}=\frac1{R_1}+\frac1{R_2}+\frac1{R_3}=\frac{L_1k_1}W+\frac{L_2k_2}W+\frac{L_3k_3}W$$
$$R_t = \frac{W}{L_1k_1 + L_2k_2 + L_3k_3}$$
7.2.7 Thermal Management of IC and PWB Packages
Top: a heat sink, using a thermally conducting grease, is used for cooling
Equivalent thermal resistance for the chip package.
7.3 Current technologies for thermal management
7.3.1 Heat Sinks
由$$q=hA(T_{s}-T_{f})$$可知，
the convective thermal resistance can be decreased, either by increasing the heat transfer coefficient or by increasing the heat transfer area.
Thus, in practical applications, an increase in the heat transfer area offers the only means to reduce the convective thermal resistance. This is accomplished through the use of extended surfaces or fins
The rectangular fin shown in Figure has a height L, width W and thickness $$\delta$$
The rectangular fin shown in Figure 6.19 has a height L, width W and thickness
The temperature of the base surface to which the fin is attached is Tb and the ambient temperature is Ta.
散热片底板面积$$A_b=W\delta$$ => $$2WL+sL\delta + W \delta$$
A rigorous analysis shows that, for the rectangular fin, the total heat transfer from the fin area can be written as:$$\mathrm{q=\eta~hA_f(T_b-T_a)}$$
where Aƒ is the base area of the fin and η is the fin efficiency which can be calculated as:$$\eta=\tanh(\mathrm{mL})/(\mathrm{mL})=\frac{e^{mL}-e^{-mL}}{e^{mL}+e^{-mL}}\quad/mL$$
And $$m=\sqrt{\frac{2h(W+\delta)}{kW\delta}}$$
The quantity m can be defined as follows:
$$m=\sqrt{\frac{hP}{kA_b}}$$
where P is the perimeter of the fin shape, and Ab is the cross-sectional area of the base of the fin.
7.3.2 *Thermal Vias
Thermal vias embedded in the board may help to reduce the resistance to heat flow, especially in the direction perpendicular to the plane of the PWB.
7.3.3 *Heat Pipe Cooling
7.3.4 Jet Impingement Cooling
Jet impingement has been widely used in many applications where high convective heat transfer rates are required.
In confined jet impingement, the spent fluid from a single nozzle, or an array of nozzles, flows outward in a narrow channel bounded by the plate containing the nozzle and the impingement surface.
7.3.5 Immersion Cooling
Thermal control of operational electronic components by direct immersion, in low boiling point dielectric liquids, dates back to the late 1940s.
In the mid-1980s, use of immersion cooling for the Cray 2 and ETA-10 supercomputers, as well as substantial research on jet impingement and spray cooling, led to renewed interest in this technology.
Due to the elimination of the solid-solid interface resistance, immersion cooling is well suited to the cooling of advanced electronic systems now under development.
In (a), a ‘‘remote’’ condenser, external to the electronic enclosure and cooled by water, air, or other fluid, condenses the vapor leaving the enclosure and directs the condensate back to the enclosure for reuse.
In (b), the condenser is located in the vapor space above the liquid, producing a more compact immersion module design, and the condensate drips back into the liquid
Due to the high solubility of air in the perfluorinated fluorocarbons, often used as immersion cooling liquids, it is not uncommon for vapor space condensers to be adversely affected by a buildup of noncondensable gas. Such difficulties can be avoided by submerging the condenser (heat exchanger tubes) in the liquid as shown in (a)
As a further modification of this approach, it is possible to use the side and top walls of the liquid-filled enclosure to serve as the submerged condenser, which can then be externally air-cooled or liquid-cooled, as shown in (b).
Immersion cooling is one of the most reliable thermal management techniques, since it eliminates the problematic solid-solid interface, and since all the components reside in a completely sealed liquid environment.
7.3.6 Thermoelectric Cooling
The Peltier Effect is the basis for the thermal electric cooler (TEC), which is a solidstate heat pump.
If a potential is placed across two junctions, heat will be absorbed into one junction, and expelled from the other, in proportion to the current.
Most material combinations exhibit the Peltier Effect to some degree.
However, it is most obvious across a p-n junction as shown in figure.
As electrons are transported from the p-side of a junction to the n-side, they are elevated to a higher energy state and thus absorb heat, resulting in cooling the surrounding area. When they are transported from the p-side to the n-side, they release heat.
A TEC device is constructed by placing one to several hundred thermocouples electrically in series, and thermally in parallel, between two pieces of metallized, thermally conductive ceramic acting as an electrical insulator.
8.1 introduction to SOC/SIP/SOP
- SIP
Def: a combination of multiple active electronic components of different functionality, assembled in a single unit, which provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components, and other packages and devices.
8.2 Difficult challenges for SiP, SiP Thermal Management
System integration is aimed at higher performance, miniaturization, heterogeneous integration, and eventual cost reduction at the package level. Many critical technology challenges must be solved to achieve the ultimate performance goals and other benefits of SiP. The difficult challenges for SiP are presented in Table below.
8.3 System Package
8.3.1 SoC (System-on-Chip) and SiP (System-in-Package)
SoC refers to a very large-scale IC, which integrates an electronic system on a single chip. The embedded electronic system can combine all needed functions, including microprocessor, memory, optical, oscillator, and often radio-frequency, etc.
SoC has a couple of advantages. Normally the overall performance for SoC is better than SiP due to the compact connection.
Issues posed by SoC technology, such as very high design and prototyping cost, long development cycle time.
Given the high cost of SoC early development, SiP provides an alternative method to make up a complete electronic system. In contrast to SoC, SiP incorporates multiple chips into a single package. Each incorporated chip handles a part of functions in the whole system, and the combined system can operate the same as if it was integrated by SoC.
SIP is a broader sense of an old concept called multi-chip-module (MCM). MCM normally refers to assembly of multiple chips side-by-side on a single ceramic substrate using traditional connecting processes, such as wire bonding and flip chip. SiPs can be found in mobile, internet of things (IoT) and wireless combo applications.
Regarded as the next level of MCM technology, SiP is designed with the ability to assembly multiple chips not only horizontally, but vertically as well. The above-mentioned 3D die stacking and package stacking technology are encompassed in the concept of SiP.
With SiP technology, electronic companies can drastically reduce development time and risk, which overcomes the limitations of SoC development.
SoC and SiP have their own pros and cons. It’s believed that SoC is more suitable for high volume production of systems with low complexity. And SiP is a good choice for low volume production of high complex systems.
8.3.2 System-on-Chip (SoC) Test
SoC technology is based on using embedded cores to reduce time-to-market and save overall cost of the chip. These embedded cores may have been designed by different vendors, may have varying degrees of readiness for reuse in SoC design and may have been developed at a different time from the SoC that will use them.
8.3.3 3D Packaging
8.3.4 UTCP
The UTCP can be used independently or serves as an interposer, which can be further embedded inside PCB or FCB (flexible circuit board) and replace the needs for directly embedding of bare die. The KGD problem is solved, because the functionality of UTCP can be easily tested before embedding it in the main board. Fig. 7.4 shows a functional electrocardiography (ECG) measurement circuit, where a TI microcontroller was packaged using UTCP technology and embedded inside FCB.
8.4 Introduction to CSP and WLP, WLP Technologies, and Reliability
8.4.1 SCP,WLP (Single-Chip Wafer-Level packaging)
The single-chip WLP is similar to a Chip-scale package (CSP) in package configuration.
The main difference btw a single-chip WLP and a CSP is the packaging assembly process. Single-chip WLPs are made using wafer-level packaging technology in which the interconnection bumping and testing is performed on the wafer.
The common and pervasive requirements in all of electronics are (1) ultra-low-cost, (2) thin, light, and portable, (3) very high performance, (4) diverse functions involving a variety of semiconductor chips and packaging, and (5) user friendliness.
8.4.2 CSP (Chip Scale Package)
The trend in microelectronics has been toward ever-increasing numbers of I/Os on packages, which is, in turn, driving the packaging configuration of semiconductors.
CSP can combine the strengths of various packaging technologies, such as the size and performance advantage of bare die assembly and the reliability of encapsulated devices.
Advantages of CSP
smaller size (reduced footprint and thickness)
lesser weight
a relatively easier assembly process
lower overall production costs
improvement in electrical performance.
8.4.3 Fan-in and Fan-out
This figure shows the purpose of microelectronics package from BGA to wafer level package (WLP)-molded and a more recent fan-out configurations. An interposer is used to accommodate the fine pitch of the chip as well as the next level interconnection, e.g. PCB.
- FI-WLP (Fan-in Wafer-Level Package)
–refers to the technology of packaging an IC at the wafer level, instead of the traditional process of assembling individual dies into packages after dicing them from a wafer.
–an extension of the wafer fabrication process and uses the traditional fabrication processes and tools.
- FO-WLP (Fan-out Wafer)
–an enhancement of standard WLPs, enabling a greater number of I/O connections.
–This package involves dicing chips from a silicon wafer, precisely positioning the KGD (known-good-die) on a “reconstituted” or “carrier” wafer / panel, which is then molded.
Fan-in is mainly applied to the mobile market (90% of its market)
Fan-out has also found applications in the high-end market (networking and computing applications) due to its ability to address higher I/O count and larger package form factors; it also has improved reliability performance and increased capability for 3D integration using PoP (Package on Package) and SiP heterogeneous integration.
This Fig shows single-chip microelectronic packaging technologies into three key technologies: (1) plastic ball grid arrays (PBGAs), (2) ceramic column grid arrays (CGAs or CCGAs), and (3) and smaller foot-print wafer-level packages. PBGAs and chip scale packages (CSPs) are now widely used for many commercial electronic applications, including portable and telecommunication products.
8.5 WLP
8.5.1 Overview
- Definition
WLP is IC packaging formed at the wafer level on the wafer in the wafer foundry. This is in contrast to conventional packaging that is done in two parts — wafer and singulation of that wafer into ICs and the subsequent packaging of these ICs into QFP, BGA, CSP or other packages.
工艺思路：
\1. 先在圆片上完成IC加工
\2. 才有一定工艺直接在圆片上加工出IC互连接口
\3. 利用该接口进行测试、老化
\4. 再分割圆片，直到得到IC成品
WLP provides many benefits — the two most important being the lowest cost and smallest size.
- WLP Pros:
Smallest system size, because it is truly a chip size package
Enabling interconnect continuum from IC to PWB because of thin-film processing
Reduced cost of packaging, because all the connections are done at wafer level
Reduced cost of testing, because testing is done at the wafer level once for all ICs
Reduced cost of burn-in, because the burn-in is done at the wafer level once
Elimination of underfill because of compliancy of the leads or other ways to achieve reliability
Improved electrical performance because of short lead lengths
- WLP Cons:
与PWB不兼容
Since the interconnect must be located in the active area of the die, very high I /O ICs would require very small solder balls on very tight pitch.
Figure shows an area array of 30 micron solder balls on 100 micron pitch. It is technically feasible to manufacture such small solder balls, they would require very high density PWB to interconnect, but it is very expensive.
The tightest board pitch currently in use today is 0.5 mm or 500 microns. So, the board pitch will have to be improved to 100 microns, requiring 25 micron lithography technology to be manufactured on a very large board.
失效IC封装
WLP的焊球互连
The two most important factors driving the WLP are size benefits for portable products and cost benefits for all products.
Lower cost and higher performance cannot be achieved without major changes in architecture, materials and manufacturing processes. Today, these new technologies include SiP, wafer level packaging (WLP), wafer thinning, and through silicon vias (TSVs). In the near future, we will see additional changes with the incorporation of nanomaterials.
The consumer’s demand for thin multifunctional products has led to increased pressure on alternative high density packaging technologies. High-density three-dimensional (3D) packaging of complete functional blocks has become the major challenge in the industry:
RF System-in-Package (SiP) applications have become the technology driver for small components, packaging, assembly processes, and high-density substrates.
The use of motion-gesture sensors in various consumer and portable devices has expanded the MEMS
Performance requirements such as increased bandwidth and lower power are driving 3D ICs designed with through silicon vias (TSV).
8.5.2 WLP Technologies
WLP can integrate package process in wafer fab, which provides a streamline from the silicon start to customer shipment. The WLP cross section and a close-up backside image are presented in Fig. 8.6.
Sequence of processes from a bare wafer to IC fabrication to wafer-level packaging to burn-in and test to scribing into individual ICs to system board assembly. The burn-in and test at wafer level is a very important part of the WLP, since it allows all the ICs to be tested while still in wafer form, known good packages (KGP).
从空白圆片开始，经过IC加工，到圆片级封装、老化、测试，最后分割成单个IC成品进行系统电路板组装。
As can be seen, WLP does not use an interposer, and the solder balls are realized on the chip by wafer level processing. The solder ball pad is routed within the chip outline from the chip perimeter contact pad, which is so called a “fan-in” design. The ball pitch can be as small as 0.3 mm. But, as the WLP is directly mounted on PCB, ball pitch larger than 0.4 mm is necessary to ensure high yield and reliability.
Another limitation of WLP is the number of I/O count. Since the package area and ball pitch are confined, the total number of I/O count is normally no more than 100.
8.5.3 WLP Reliability
The WLP reliability is achieved by one of several ways. The fundamentals of reliability are based on what is called Coffin-Manson or modified equation, which predicts that the thermal fatigue lifetime of a solder joint is proportional to the square of the bump height or standoff.
Four ways to provide a reliable connection:
Compliant connection. 柔性互联结构 This concept provides an excellent reliability as with PGAs between IC package and the board (used for over 30 years). Wirebonding reliability is also based on this concept where the stresses are taken up by the compliant leads. 可以降低应力
Stacking solders. 满足高度需求，提高焊球的疲劳寿命
Increased solder ball size, the net effect of which is similar to the stacked solder balls in achieving the increased height.
TCE-matched, having matched thermal expansion of silicon IC and the board.
8.5.3.1 Underfills are filled epoxy resins.
8.5.4 Wafer-level Burn-in and Test
Wafer-level burn-in and tests are a necessity for the adoption of low-cost WLP.
Non-destructive probing technologies have been developed to deal with wafer-level testing and burn-in of bumped wafers.
- In the VS-contact technology, shown in Figure 8.8, the connection is made between the substrate and the wafer with an interposer composed of conductive isotropic rubber and a flexible polyimide sheet containing Ni plated vias that match up with the bumped wafer surface. Electrical testing is accomplished through these contacts. Microspring contact technology uses a controlled shape and height spring element. The microspring contact has been used previously on probe cards to test contact at Al wirebond pads, Au pads and solder balls.
- 微弹簧接触技术 通过弹簧单元补偿待测位置间的高度差异
9. Additional Lecture
9.1 Electronic Packaging Technology
The electronic packaging has six functions:
Signal distribution, involving topological and electromagnetic considerations;
Power distribution, involving electromagnetic, structural, and material aspects;
Heat dissipation (thermal management), involving structural and material considerations;
Support and protection (mechanical, chemical, and electromagnetic) components and interconnections from the hostile environments;
Design (for performance, environment, manufacture ability, and reliability) at the front end and system test at the final stage prior to the system shipment;
System testing that involves every aspect of system reliabilities.
9.2 Chip Connection: Wire Bonding, TAB Structure, Flip-Chip
- Wire Bonding
- TAB
- Flip-Chip
FC Advantages:
Smaller size, increased functionality, Improved
performance, Most rugged (high reliability), Improved thermal
capabilities, Low cost
FC Assembly
9.3 Introduction to 3D Packages, Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP).
9.4 BGA, CSP, WLA
BGA: with 1.27-mm pitch (distance between adjacent ball centers) and finer pitch versions with 1- and 0.8-mm pitches, are the only choice for packages with higher than 300 I/O counts, replacing leaded packages such as the quad flat pack (QFP). BGAs provide improved electrical and thermal performance, more effective manufacturing, and ease-of-handling compared to conventional surface mount (SMT) leaded parts.
Finer pitch area array packages (FPBGA), also known as CSPs, are further miniaturized versions of BGAs, or smaller configurations of leaded and leadless packages with features generally less than 0.8-mm pitches.
CSP: An improvement in packaging efficiency beyond BGAs is achieved by CSP. Most CSPs use substrate (interposer) or metal layer to redistribute the very fine-pith (as small as 0.075 mm) peripheral pads on the chip to a much larger pitch (1 mm, 0.8 mm, 0.75 mm, and 0.5 mm) area array pads on the PWB.
WLP: the technology employed for the fabrication of ICs while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. This technique has grown rapidly in popularity in the IC industry due to advantages in terms of component size as well as production time and cost. WLP is essentially a type of chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die.